1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and relates particularly to a semiconductor integrated circuit device comprising an internal power supply circuit for converting a power supply voltage from an external source to a particular voltage and supplying the converted voltage to the internal circuits of the semiconductor integrated circuit device.
2. Description of the Prior Art
FIG. 16 is a block diagram of a 64 Mbit.times.8 synchronous DRAM device according to the prior art.
As shown in FIG. 16, the synchronous DRAM (SDRAM below) 200 device comprises an internal power supply circuit 205, address buffer 206, control signal buffer 207, clock buffer 208, four memory array banks 209, 210, 211, and 212, input/output (I/O) buffer 213 for data input and output, and a control circuit 215 comprising mode register 214 and controlling the memory array banks 209-212 and I/O buffer 213. The internal power supply circuit 205 comprises an internal voltage step-down circuit 201, substrate voltage generator 202, step-up voltage generator 203, and reference voltage generator 204.
The internal voltage step-down circuit 201 drops the power supply voltage from an external source to power supply terminal Vcc to produce the internal power supply voltage int.Vcc supplied to the internal circuits of the SDRAM 200. The value of internal power supply voltage int.Vcc is determined according to the reference voltage Vref input from the reference voltage generator 204. More specifically, the internal voltage step-down circuit 201 controls and outputs the internal power supply voltage int.Vcc at the level of the reference voltage Vref supplied from the reference voltage generator 204.
The substrate voltage generator 202 generates and outputs the bias voltage of the semiconductor substrate, and applies a negative substrate voltage Vbb to the semiconductor substrate.
The step-up voltage generator 203 steps up the power supply voltage from the power supply terminal Vcc to generate and supply step-up voltage Vpp to each of the memory array banks 209-212.
The address buffer 206 is connected to the address signal input terminals to which the address signals are input from an external source. These input terminals may include, for example, bank address terminals BA0 and BA1 from which the bank address selection signals are input, and the address terminals A0-A11 through which the address signals are input.
The control signal buffer 207 is connected to each of the control signal input terminals through which the control signals are input from external sources. These control signal input terminals include in this example the /CS terminal to which the chip selector signal is input, the /RAS terminal to which the row address strobe signal is input, the /CAS terminal to which the column address strobe signal is input, the /WE terminal to which the write enable signal is input, and the DQM terminal to which the I/O mask signal is input.
The clock buffer 208 generates the internal clock signal INTCLK from the externally supplied clock signal, and supplies the clock signal to the connected address buffer 206, control signal buffer 207, I/O buffer 213, and control circuit 215. The external clock signal is supplied to the clock buffer 208 through the CLK terminal, and the clock enable signal is supplied to the clock buffer 208 through the CKE terminal.
The control circuit 215 is connected to each of the memory array banks 209-212, the address buffer 206, the control signal buffer 207, and the I/O buffer 213. The mode register 214 is used by the control circuit 215 when determining the burst length from the address signals input from the address signal input terminals.
Current consumption is high when the frequency of the internal clock signal INTCLK is high compared with current consumption when the internal clock signal INTCLK is low, and the drop in the internal power supply voltage int.Vcc and step-up voltage Vpp output from the internal voltage step-down circuit 201 and step-up voltage generator 203 thus increases.
In addition, the negative substrate voltage Vbb output from the substrate voltage generator 202 tends to be higher when the frequency of the internal clock signal INTCLK is high compared with when the internal clock signal INTCLK is low.